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? semiconductor components industries, llc, 2003 october, 2003 ? rev. 2 1 publication order number: ntp18n06/d ntp18n06, ntb18n06 power mosfet 15 amps, 60 volts n?channel to?220 designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. typical applications ? power supplies ? converters ? power motor controls ? bridge circuits maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain?to?source voltage v dss 60 vdc drain?to?gate voltage (r gs = 10 m w ) v dgr 60 vdc gate?to?source voltage ? continuous ? non?repetitive (t p 10 ms) v gs 20 30 vdc drain current ? continuous @ t c = 25 c ? continuous @ t c = 100 c ? single pulse (t p 10 s) i d i d i dm 15 8.0 45 adc adc a pk total power dissipation @ t c = 25 c derate above 25 c p d 48.4 0.32 watts w/ c operating and storage temperature range t j , t stg ?55 to +175 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 10 vdc, v ds = 60 vdc, i l(pk) = 11 a, l = 1.0 mh, r g = 25 w ) e as 61 mj thermal resistance ? junction?to?case ? junction?to?ambient r q jc r q ja 3.1 72.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 15 amperes 60 volts r ds(on) = 90 m w device package shipping ordering information ntp18n06 to?220ab 50 units/rail to?220ab case 221a style 5 1 2 3 4 n?channel d s g marking diagrams & pin assignments ntx18n06 = device code x = b or p ll = location code y = year ww = work week ntx18n06 llyww 1 gate 3 source 4 drain 2 drain ntx18n06 llyww 1 gate 3 source 4 drain 2 drain 1 2 3 4 d 2 pak case 418aa style 2 ntb18n06 d 2 pak 50 units/rail ntb18n06t4 d 2 pak 800/tape & reel http://onsemi.com
ntp18n06, ntb18n06 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?to?source breakdown voltage (note 1) (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 60 ? 67 62.4 ? ? vdc mv/ c zero gate voltage drain current (v gs = 0 vdc, v ds = 60 vdc) (v gs = 0 vdc, v ds = 60 vdc, t j = 150 c) i dss ? ? ? ? 1.0 10 m adc gate?body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics (note 1) gate threshold voltage (note 1) (v ds = v gs, i d = 250 m adc) threshold temperature coefficient (negative) v gs(th) 2.0 ? 2.9 6.2 4.0 ? vdc mv/ c static drain?to?source on?resistance (note 1) (v gs = 10 vdc, i d = 7.5 adc) r ds(on) ? 76 90 m w static drain?to?source on?voltage (note 1) (v gs = 10 vdc, i d = 15 adc) (v gs = 10 vdc, i d = 7.5 adc, t j = 150 c) v ds(on) ? ? 1.2 1.08 1.62 ? vdc forward transconductance (note 1) (v ds = 7.0 vdc, i d = 6.0 adc) g fs ? 6.8 ? mhos dynamic characteristics input capacitance (v 25 vd v 0vd c iss ? 325 450 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss ? 108 150 reverse transfer capacitance f = 1 . 0 mhz) c rss ? 34 70 switching characteristics (note 2) turn?on delay time t d(on) ? 10 15 ns rise time (v dd = 30 vdc, i d = 15 adc, v gs =10vdc t r ? 25 70 turn?off delay time v gs = 10 vdc, r g = 9.1 w ) (note 1) t d(off) ? 14 50 fall time r g 9.1 w ) (note 1) t f ? 13 50 gate charge (v 48 vd i 15 ad q t ? 12 22 nc (v ds = 48 vdc, i d = 15 adc, v gs = 10 vdc ) ( note 1 ) q 1 ? 4.1 ? v gs = 10 vdc) (note 1) q 2 ? 4.5 ? source?drain diode characteristics diode forward on?voltage (i s = 15 adc, v gs = 0 vdc) (note 1) (i s = 15 adc, v gs = 0 vdc, t j = 150 c) v sd ? ? 0.95 0.84 1.15 ? vdc reverse recovery time t rr ? 35 ? ns (i =15adc v = 0 vdc t a ? 27 ? (i s = 15 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) (note 1) t b ? 7.4 ? reverse recovery stored charge di s /dt = 100 a/ m s) (note 1) q rr ? 0.050 ? m c 1. pulse test: pulse width = 300 m s, duty cycle = 2%. 2. switching characteristics are independent of operating junction temperature.
ntp18n06, ntb18n06 http://onsemi.com 3 figure 1. on?region characteristics v ds , drain?to?source voltage (volts) 32 24 16 8 4 3 2 1 0 figure 2. transfer characteristics v gs , gate?to?source voltage (volts) 7 6 5 4 3 32 24 16 8 0 0 figure 3. on?resistance versus gate?to?source voltage i d , drain current (amps) 0.2 0.16 0.12 0.04 20 16 12 8 4 0 figure 4. on?resistance versus drain current and gate voltage 0 figure 5. on?resistance variation with temperature t j , junction temperature ( c) 2 1.6 1.4 1.2 1 0.8 150 125 100 75 50 25 0 ?25 ?50 v ds , drain?to?source voltage (volts) 10 0 100 10 1 0.6 1000 figure 6. drain?to?source leakage current versus voltage i d , drain current (amps) i d , drain current (amps) r ds(on) , drain?to?source resistance ( ) 32 28 0.08 r ds(on) , drain?to?source resistance ( ) r ds(on), drain?to?source resistance (normalized) i dss , leakage (na) 20 60 5 40 30 50 v gs = 10 v t j = 25 c t j = ?55 c t j = 100 c v ds 10 v t j = 25 c t j = ?55 c t j = 100 c v gs = 10 v i d = 7.5 a v gs = 10 v t j = 150 c v gs = 0 v t j = 100 c 9 v 8 v 7 v 6.5 v 6 v 5.5 v 5 v 4.5 v 8 24 0.2 0.16 0.12 0.04 20 16 12 8 4 0 0 32 28 0.08 t j = 25 c t j = ?55 c t j = 100 c v gs = 15 v 24 175 1.8 i d , drain current (amps)
ntp18n06, ntb18n06 http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when calculating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. 10 0 10 15 20 25 gate?to?source or drain?to?source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 900 300 100 0 v gs v ds 500 200 55 400 v gs = 0 v v ds = 0 v t j = 25 c c iss c oss c rss c iss 600 700 800 c rss
ntp18n06, ntb18n06 http://onsemi.com 5 16 0 0.6 drain?to?source diode characteristics v sd , source?to?drain voltage (volts) figure 8. gate?to?source and drain?to?source voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance ( w ) 1 10 100 1000 1 t, time (ns) v gs = 0 v t j = 25 c figure 10. diode forward voltage versus current v gs , gate?to?source voltage (volts) 0 10 6 2 0 q g , total gate charge (nc) 12 8 4 48 10 210 612 0.68 0.76 1 4 8 12 i d = 15 a t j = 25 c v gs q 2 q 1 q t t r t d(off) t d(on) t f v ds = 30 v i d = 15 a v gs = 10 v 0.84 0.92 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance ? general data and its use.o switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r q jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain?to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
ntp18n06, ntb18n06 http://onsemi.com 6 safe operating area figure 11. maximum rated forward biased safe operating area t, time (s) 0.1 1.0 0.01 110 0.1 0.01 0.001 0.0001 0.000001 t j , starting junction temperature ( c) e as , single pulse drain?to?source figure 12. maximum avalanche energy versus starting junction temperature 0.1 1 100 v ds , drain?to?source voltage (volts) figure 13. thermal response 1 100 avalanche energy (mj) i d , drain current (amps) r ds(on) limit thermal limit package limit 0.1 0 25 50 75 100 125 20 i d = 11 a 10 10 175 figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 40 80 v gs = 20 v single pulse t c = 25 c 60 1 ms 100 m s 10 ms dc 10 m s 150 r(t), transient thermal resistance 0.00001 d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse
ntp18n06, ntb18n06 http://onsemi.com 7 information for using the d 2 pak surface mount package recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. mm inches 0.33 8.38 0.08 2.032 0.04 1.016 0.63 17.02 0.42 10.66 0.12 3.05 0.24 6.096
ntp18n06, ntb18n06 http://onsemi.com 8 solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. solder stencils are used to screen the optimum amount. these stencils are typically 0.008 inches thick and may be made of brass or stainless steel. for packages such as the sc?59, sc?70/sot?323, sod?123, sot?23, sot?143, sot?223, so?8, so?14, so?16, and smb/smc diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. this is not the case with the dpak and d 2 pak packages. if one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or atombstoningo may occur due to an excess of solder. for these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. the opening for the leads is still a 1:1 registration. figure 15 shows a typical stencil for the dpak and d 2 pak packages. the pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ?? ?? ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? figure 15. typical stencil for dpak and d 2 pak packages solder paste openings stencil soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * due to shadowing and the inability to set the wave height to incorporate other surface mount components, the d 2 pak is not recommended for wave soldering.
ntp18n06, ntb18n06 http://onsemi.com 9 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177?189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joint. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 16. typical solder heating profile
ntp18n06, ntb18n06 http://onsemi.com 10 package dimensions d 2 pak case 418aa?01 issue o style 2: pin 1. gate 2. drain 3. source 4. drain seating plane s g d ?t? m 0.13 (0.005) t 23 1 4 3 pl k j v e c a dim min max min max millimeters inches a 0.340 0.380 8.64 9.65 b 0.380 0.405 9.65 10.29 c 0.160 0.190 4.06 4.83 d 0.020 0.036 0.51 0.92 e 0.045 0.055 1.14 1.40 g 0.100 bsc 2.54 bsc j 0.018 0.025 0.46 0.64 k 0.090 0.110 2.29 2.79 s 0.575 0.625 14.60 15.88 v 0.045 0.055 1.14 1.40 ?b? m b w w notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. f 0.310 ??? 7.87 ??? m 0.280 ??? 7.11 ??? m f m f m f variable configuration zone u view w?w view w?w view w?w 123
ntp18n06, ntb18n06 http://onsemi.com 11 package dimensions to?220 case 221a?09 issue aa notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 --- 1.15 --- z --- 0.080 --- 2.04 b q h z l v g n a k f 123 4 d seating plane ?t? c s t u r j style 5: pin 1. gate 2. drain 3. source 4. drain
ntp18n06, ntb18n06 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ntp18n06/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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